Field of the Invention
The embodiments discussed herein relate to a semiconductor device and a method of manufacturing a semiconductor device.
Description of the Related Art
Conventionally, silicon (Si) is used as a constituent material of a power semiconductor device that controls high voltage and/or large current. There are several types of power semiconductor devices such as bipolar transistors, insulated-gate bipolar transistors (IGBTs), and metal oxide semiconductor field effect transistors (MOSFETs). These devices are selectively used according to intended purpose.
For example, bipolar transistors and IGBTs have high current density compared to MOSFETs, and can be adapted for large current but cannot be switched at high speed. In particular, the limit of switching frequency is about several kHz for bipolar transistors and about several tens of kHz for IGBTs. On the other hand, power MOSFETs have low current density compared to bipolar transistors and IGBTs, and are difficult to be adapted for large current but can be switched at high speed up to about several MHz.
However, there has been a strong demand in the market for a power semiconductor device achieving both large current and high speed. Thus, IGBTs and power MOSFETs have been intensively developed and improved, and the performance of power devices has substantially reached the theoretical limit determined by the material. In terms of power semiconductor devices, semiconductor materials replacing silicon have been investigated and silicon carbide (SiC) has been focused on as a semiconductor material enabling production (manufacture) of a next-generation power semiconductor device with low on voltage, high-speed characteristics, and high-temperature characteristics (see, for example, K. Shenai, et al, “Optimum Semiconductors for High-Power Electronics”, IEEE Transactions on Electron Devices, September 1989, Vol. 36, No. 9, pages 1811-1823).
Silicon carbide is chemically a very stable semiconductor material, has a wide band gap of 3 eV, and can be used very stably as a semiconductor even at high temperatures. Silicon carbide has a critical electric field strength that is ten times that of silicon or greater, and thus is expected to be a semiconductor material that can sufficiently reduce on-resistance. These merits of silicon carbide are common to other wide band gap semiconductors (hereinafter, wide band gap semiconductor) with a band gap greater than silicon, such as gallium nitride (GaN). Thus, a high-voltage semiconductor device can be achieved by using a wide band gap semiconductor (see, for example, B. Jayant Baliga, “Silicon Carbide Power Devices”, U.S.A, World Scientific Publishing Co., Mar. 30, 2006, page 61).
In such high-voltage semiconductor devices, high voltage is not only applied to an active region in which device structures are formed and current flows in an on-state but also to an edge termination region surrounding the periphery of the active region and preventing breakdown voltage. Electric field concentrates in the edge termination region. The breakdown voltage of a high-voltage semiconductor device is determined by the impurity concentration, the thickness, and electric field strength of the semiconductor. The resistance to breakdown determined in this manner by semiconductor-specific characteristics is constant from the active region to the edge termination region. Therefore, consequent to the concentration of electric field at the edge termination region, the edge termination region is at risk of being subject to an electrical load that exceeds the resistance to breakdown, leading to destruction. In other words, the breakdown voltage of a high-voltage semiconductor device is limited by the resistance to breakdown at the edge termination region.
As a device that improves the breakdown voltage of a high-voltage semiconductor device overall by distributing or mitigating the electric field of the edge termination region, devices are known that dispose a breakdown voltage structure such as junction termination extension (JTE) structure or a field limiting ring (FLR) structure in the edge termination region (see, for example, Japanese Patent Application Laid-Open Publication Nos. 2010-50147 and 2006-165225). In Japanese Patent Application Laid-Open Publication No. 2010-50147, a floating metal electrode contacting an FLR is disposed as a field plate (FP) to release charge generated at the edge termination region and thereby, improve reliability.
A MOSFET including a JTE structure will be taken as an example to describe a breakdown voltage structure of a conventional high-voltage semiconductor device. FIG. 6 is a cross-sectional view of a structure of a conventional semiconductor device. A conventional semiconductor device depicted in FIG. 6 includes on a semiconductor base body formed from silicon carbide (hereinafter, silicon carbide base body (semiconductor chip)) 140, an active region 110 and an edge termination region 120 surrounding the periphery of the active region 110. The silicon carbide base body 140 is an n+-type supporting substrate formed from silicon carbide (hereinafter, n+-type silicon carbide substrate) 101 on which an n−-type semiconductor layer formed from silicon carbide (hereinafter, n−-type silicon carbide layer) 102 and a p-type semiconductor layer formed from silicon carbide (hereinafter, p-type silicon carbide layer) 104 are sequentially stacked on a front surface of the n+-type silicon carbide substrate 101.
In the active region 110, a metal oxide semiconductor (MOS) gate structure is disposed on a front surface (surface on the p-type silicon carbide layer 104 side) side of the silicon carbide base body 140. The p-type silicon carbide layer 104 is removed from the entire edge termination region 120, whereby on the front surface of the silicon carbide base body 140, a recess 121 is formed that makes the edge termination region 120 lower than the active region 110 (recessed toward the drain side) and the n−-type silicon carbide layer 102 becomes exposed at a bottom 121a of the recess 121. In the edge termination region 120, a JTE structure 130 is disposed that includes multiple adjacent p−-type low-concentration regions having progressively lower impurity concentrations the farther the p−-type low-concentration region is disposed toward the outer side (chip edge side) (two in the present example, indicated by reference numerals 131, 132 and assumed to be a p−-type and a p−−-type sequentially from an inner side of the edge termination region 120) arranged adjacently.
The p−-type low-concentration region (hereinafter, first JTE region) 131 and the p−−-type low-concentration region (hereinafter, second JTE region) 132 are each selectively disposed in the n−-type silicon carbide layer 102, at a portion exposed at the bottom 121a of the recess 121. At the bottom 121a of the recess 121, the first JTE region 131 contacts an outermost p-type base region 103. The JTE structure 130 and a portion 103a of the p-type base region 103, extending into the bottom 121a of the recess 121 form the breakdown voltage structure. A drain electrode 115 contacting a back surface of the silicon carbide base body 140 (back surface of the n+-type silicon carbide substrate 101) is disposed. Reference numerals 105 to 109, and 111 to 114 indicate an n+-type source region, a p+-type contact region, an n-type JFET region, a gate insulating film, a gate electrode, a field oxide film, an interlayer insulating film, a source electrode, and a passivation film, respectively.
In the MOSFET having the structure depicted in FIG. 6, when a positive voltage with respect to the source electrode 113 is applied to the drain electrode 115 and a voltage lower than the threshold voltage is applied to the gate electrode 109, a pn junction between a p-type base region 104a and an n-type JFET region 107 becomes reverse biased, the reverse breakdown voltage of the active region is not reached, and no current flows. The p-type base region 104a is a portion of the p-type silicon carbide layer 104, excluding the n+-type source region 105 and the p+-type contact region 106.
On the other hand, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 109, an n-type inversion layer (channel) is formed at the surface layer of a portion of the p-type base region 104a directly beneath the gate electrode 109 (drain side). Consequently, current flows through a path of the n+-type silicon carbide substrate 101, the n−-type silicon carbide layer 102, the n-type JFET region 107, the inversion layer on the surface of the p-type base region 104a, and the n+-type source region 105. Thus, a commonly known MOSFET switching operation may be performed by controlling the gate voltage.
Further, in the MOSFET having the structure depicted in FIG. 6, when voltage is applied, a depletion layer spreads outwardly from a pn junction between the p-type base region 103 and an n−-type drift layer, to both the first and second JTE regions 131, 132. The n−-type drift layer is a portion of the n−-type silicon carbide layer 102, excluding the p-type base region 103 and the first and second JTE regions 131, 132. The breakdown voltage at the edge termination region is sustained by a pn junction between the first and second JTE regions 131, 132 and the n−-type drift layer.
As another high-voltage semiconductor device, a device has been proposed in which on the front surface of a silicon carbide base body, a recess is formed where the edge termination region is lower than the active region, and a p-type region forming a breakdown voltage structure is disposed to cover a boundary of a side wall and bottom of the recess (hereinafter, bottom corner portion of the recess) (see, for example, Japanese Patent Application Laid-Open Publication Nos. 2010-045388, 2002-164541, and 2014-107500).